1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and in particular to a structure of an SRAM (Static Random Access Memory) and a method of manufacturing the same.
2. Description of the Background Art
Static random access memories have been known as a kind of semiconductor memory devices. FIG. 18 is an equivalent circuit diagram showing one memory cell in an SRAM. Referring to FIG. 18, the memory cell employs a p-type MOS (Metal Oxide Semiconductor) transistor as a load, and is formed of six transistors. More specifically, a pair of driver transistors Q1 and Q2 (n-type MOS transistors) and a pair of load transistors Q5 and Q6 (p-type MOS transistors) are mutually connected to form a flip-flop circuit.
Source regions of paired load transistors Q5 and Q6 are connected to a power supply Vcc, and source regions of driver transistors Q1 and Q2 are connected to grounds 212 and 213, respectively.
A pair of access transistors Q3 and Q4 (n-type MOS transistors) are connected to storage nodes 214 and 215, respectively. One of source/drain regions of access transistor Q3 is connected to a bit line 207, and the other of source/drain regions of access transistor Q4 is connected to a bit line 208. Gate electrodes of access transistors Q3 and Q4 are connected to a word line 209.
The SRAM includes a memory cell part and a peripheral circuitry. Peripheral circuitry serves to write information into the memory cell part and read information therefrom.
Structures of the memory cell part and peripheral circuitry in the conventional SRAM will be described below. FIG. 19 is a cross section showing the memory cell part and peripheral circuitry in the conventional SRAM.
Referring to FIG. 19, a CMOS (Complementary MOS) transistor formed of N-type and P-type MOS transistors is formed at each of the peripheral circuitry and memory cell part. More specifically, the memory cell part is provided at a main surface of a semiconductor substrate 101 with a P-type well region 102 and an N-type well region 103 neighboring to each other. An element isolating insulation film 106 located at a boundary between P-type and N-type well regions 102 and 103 is formed on the main surface of semiconductor substrate 101. A P.sup.+ -isolation region 5 is formed and buried in P-type well region 102 for preventing formation of a parasitic transistor, which may cause a problem relating to latch-up, and isolating N-type MOS transistors from each other. Similarly, N.sup.+ -isolation region 104 is formed and buried in N-type well region 103.
At predetermined regions of the main surface of P-type well region 102, there are formed a pair of N-type source/drain regions 1 spaced by a predetermined distance with a channel region 2c therebetween. A gate electrode 3c is formed on channel region 2c with a gate insulation film therebetween. Side wall insulation films 108c are formed in contact with opposite side surfaces of gate electrode 3c. Gate electrode 3c and paired N-type source/drain regions 1 form the N-type MOS transistor. At predetermined regions of the main surface of N-type well region 103, there are formed a pair of P-type source/drain regions 6 spaced by a predetermined distance with a channel region 2d therebetween. A gate electrode 3d is formed on channel region 2d with a gate insulation film therebetween. Side wall insulation films 108d are formed in contact with opposite side surfaces of gate electrode 3d. Gate electrode 3d and paired P-type source/drain regions 6 form the P-type MOS transistor.
Similarly to the memory cell part, the peripheral circuitry is provided at the main surface of semiconductor substrate 101 with P-type well region 102, N-type well region 103, element isolating insulation film 106, P.sup.+ -isolation region 5, N.sup.+ -isolation region 104, N-type source/drain regions 1, gate electrode 3a, side wall insulation films 108a and P-type source/drain regions 6.
FIGS. 20 through 29 are cross sections showing a process of manufacturing the conventional SRAM shown in FIG. 19. Referring to FIGS. 20 through 29, the process of manufacturing the conventional SRAM will be described below. FIG. 20 shows semiconductor substrate 101 of the memory cell part and peripheral circuitry. As shown in FIG. 21, an SiON film 101a is deposited on semiconductor substrate 101, and an SiN film 101b is deposited thereon.
As shown in FIG. 22, a region for forming an active region is covered with a resist 101c, and then etching is effected on SiN film 101b, SiON film 101a and semiconductor substrate 101.
As shown in FIG. 23, resist 101c is removed, and then element isolating insulation films 106 made of SiO.sub.2 are formed by the LOCOS (Local Oxidation of Silicon) method. As shown in FIG. 24, SiN film 101b and SiON film 101a are removed. In this manner, element isolating insulation films 106, which are buried more deeply at the substrate surface than the ordinary structure, are formed at the predetermined regions in the main surface of the semiconductor substrate.
Then, as shown in FIG. 25, a resist 109 is formed to cover regions at which the P-type transistors of both the peripheral circuitry and memory cell part are to be formed, and P-type wells 102 and P.sup.+ -isolation regions 5 of both the memory cell part and peripheral circuitry are formed by ion implantation.
As shown in FIG. 26, regions at which N-type transistors are to be formed are covered with resist 109, and N-type well regions 103 and N.sup.+ -isolation regions 104 are formed by ion implantation at regions for forming the P-type transistors of the memory cell part and peripheral circuitry.
As shown in FIG. 27, after forming gate electrodes 3a, 3b, 3c and 3d made of N-type polycrystalline silicon at predetermined regions on the semiconductor substrate, the regions for forming the P-type transistors of both the memory cell part and peripheral circuitry are covered with resist 109 as shown in FIG. 28. Then, using gate electrodes 3a and 3c as a mask, impurity is ion-implanted at a low concentration into regions for forming the N-type transistors of both the memory cell part and peripheral circuitry, whereby lightly doped impurity regions are formed. After removing resist 109, side wall insulation films 108a, 108b, 108c and 108d are formed in contact with opposite side surfaces of gate electrodes 3a, 3b, 3c and 3d, respectively. Using side wall insulation films 3a, 3b, 3c and 3d as a mask, ion-implantation is performed again to form heavily doped impurity regions, so that source/drain regions 1 of the LDD (Lightly Doped Drain) structure are formed. Thereafter, resist 109 is removed.
As shown in FIG. 29, regions for forming the N-type transistors are covered with resist 109, and P-type impurity is ion-implanted only into a region for forming the P-type transistor of the peripheral circuitry, whereby source/drain regions 6 are formed. Thereafter, resist 109 is removed.
In this manner, the conventional semiconductor memory device of SRAM shown in FIG. 19 is completed.
In the conventional SRAM, it is necessary to reduce plane areas occupied by respective memory cells in order to improve the degree of integration of memory cells.
For this purpose, there has been proposed a structure in which a TFT (Thin Film Transistor) is used as the P-type transistor, four elements are formed on the substrate and two elements are formed thereon, so that the cell size is reduced.
In the above structure, however, it is difficult to achieve an intended current performance of the TFT with a low voltage, and hence it is difficult to achieve stable low-voltage operation at a recently used voltage not higher than 3 V with the TFT load. In order to solve the above problem, the following reference has proposed a substrate P-type transistor having an improved performance.
More specifically, the following two problems are solved in ICICE TRANS ELECTRON, VOL. E77-C, No. 8 AUGUST 1994 "High-Density Full-CMOS SRAM Cell Technology with a deep Sub-Micron Spacing between n MOS and p MOSFET". According to the above reference, the first problem is that LOCOS isolation in the prior art cannot sufficiently reduce an isolation width between wells. By the use of trench isolation, the isolation width between wells is reduced, and thereby the cell size is reduced.
More specifically, in the conventional CMOS structure using the LOCOS isolation, if the isolation width between P-type and N-type wells is reduced, such a problem arises that parasitic thyristor operation generates latch-up. In general, the latch-up is a phenomenon that, in the bulk CMOS structure, a parasitic thyristor element is turned on and a large current flows, e.g., between power supply terminals of the CMOS circuit, so that circuit operation is impeded and/or the IC itself is destroyed. FIG. 30 shows a parasitic thyristor structure of the bulk CMOS IC having an N-type well structure. In this structure, it is assumed that a voltage lower than Vss is applied to an n.sup.+ -drain 302, and electrons are implanted from n.sup.+ -region 302 into a p-type substrate 300. Electrons are partially gathered in an n-well 303 (i.e., collector of a horizontal npn transistor Tnpn) and reach an n.sup.+ -region 304 through n-well 303. This current flows through a resistance 305 of well 303 in FIG. 30. If this current is sufficiently large and the pn junction at the source side of pMOS is biased forward due to voltage drop by resistance 305, a vertical pnp transistor 306 is turned on, and a collector current caused by holes flows through p-type substrate 300. If this current is large enough to cause the forward bias of the pn junction at the source side of nMOS transistor due to voltage drop by a resistance 309, then the horizontal npn transistor is turned on, and the collector current thereof sets pnp transistor 306 to a more deeply conductive state. While positive feedback is being applied in this manner, such a state is maintained that a large current flows between Vcc and Vss regardless of a current from an n.sup.+ -drain which initially formed a trigger. In order to escape from this state, it is necessary to cut off a current (holding current) itself flowing into a parasitic thyristor. The latch-up tends to improve characteristics of the parasitic thyristor as the CMOS IC is miniaturized to a higher extent, and this forms a serious problem in connection with densification of the CMOS IC.
Reduction the isolation width between P-type well 102 and N-type well 103 already described reduces a resistance value between these wells 102 and 103, and promotes flow of a current which causes the latch-up.
Therefore, it is necessary to keep the isolation width of a certain value or more when using the LOCOS isolation.
Meanwhile, in the case where the trench isolation is used, an isolation between the wells is deep and hence a resistance by the isolation is large, so that flow of a current causing the latch-up is suppressed. Therefore, the problem relating to the latch-up is suppressed even if the isolation width is reduced. FIG. 31 is a cross section of a general structure using the trench isolation. Isolation 150 formed of trenches completely isolates P-type and N-type wells 102 and 103 from each other through its entire thickness. Therefore, current flow between the wells is extremely suppressed as already described, so that the problem relating to latch-up is suppressed.
However, the following three problems arise in the memory cell using the trench isolation. First, the trench isolation requires a CMP (Chemical Mechanical Polishing) technique which is a highly precise flattening technique for leaving an oxide film only in the trench. Therefore, the trench isolation requires a complicated manufacturing process as compared with the conventional LOCOS isolation requiring only an etching step and an oxidation step.
Second, the trench isolation tends to form a parasitic MOS transistor at the side wall of the trench, which disadvantageously increases subthreshold leak. In order to prevent this, it is necessary to implant P.sup.+ -type impurity into the isolation portion as described below, which complicates the manufacturing process. Implantation of the P.sup.+ -type impurity is shown in FIGS. 32 and 33. FIG. 32 is a plan of an N-type MOS transistor, and FIG. 33 is a cross section taken along line 200--200 in FIG. 32. Referring to FIGS. 32 and 33, the transistor includes N-type active regions 1, trench isolation 2 and gate electrode 3. It is assumed that one of N-type active regions 1 located at left side in FIG. 32 is a drain region, and the other at the right side is a source region. At portions a1 and a2 in FIG. 32, a leak current flows as indicated by arrows in the figure. In FIG. 33, there are shown gate electrode 3, gate oxide film 4 and P.sup.+ -isolation regions 5 of isolating portion. Referring to FIG. 33, since the concentration of P.sup.+ -type impurity is low at portions a1 and a2 in FIG. 33, a current flows even if the gate electrode is lower than the threshold voltage, so that a P.sup.+ -leak current flows. In order to prevent this leak current, it is necessary to implant newly P.sup.+ -type impurity into portions a1 and a2.
Third, the trench isolation tends to cause a junction leak current as compared with the LOCOS isolation. In order to suppress this, it is necessary to round the corner of the trench isolating portion by oxidation and/or to provide a tapered trench, which complicates the manufacturing process.
As described above, if the trench isolation is used instead of the LOCOS isolation in order to reduce plane areas occupied by memory cells, various problems described above arise.